This invention relates to systems and methods of converting a data stream from one clocking domain to another.
In many computing and communication environments it is often necessary to convert a data stream from one clocking domain to another. For example, data typically is transmitted within an electronic device (e.g., a computer) in a parallel, relatively low-speed clocking domain, whereas data typically is transmitted between electronic devices in a serial, relatively high-speed clocking domain, especially over longer distances. Typically, serial-to-parallel converters (or deserializers) are used to convert serial data streams into parallel data streams and parallel-to-serial converters (or serializers) are used to convert parallel data streams into serial data streams. The data rate (or information rate) is equal to the product of the number of word bits transmitted in parallel and the word transmission rate. For serializers and deserializers the data rate at the input typically is the same as the data rate at the output. Accordingly, the input clocking rate typically is slower than the output clocking rate for a serializer, whereas the input clocking rate typically is faster than the output clocking rate for a deserializer.
Some serializers and deserializers operate at the serial clocking rate. Other serializers and deserializers include multiple channels, which allow-these circuits to operate at a fraction (e.g., one-half or one-quarter) of the serial clocking rate. These systems may be implemented with less expensive circuits that operate at lower power relative to serializers and deserializers that operate at the higher serial clocking rate.
The invention features systems and methods of converting a data stream from one clocking domain to another.
In one aspect of the invention, a clocking domain conversion system includes an input, an output, a routing circuit, and a clock generator. The input is operable to simultaneously load N input bits during each load cycle at an average rate RIN, wherein N has an integer value of at least 1. The output is operable to simultaneously output M output bits during each output cycle at an average rate ROUT, wherein M has an integer value of at least 1 and Mxe2x89xa0N. The routing circuit is operable to route the N input bits from the input to the output at a clocking rate RCLK and with a dividing ratio K of the routing circuit data rate relative to the higher of the input and output data rates, given by   K  =            N      ·              R        CLK                    M      ·              R        OUT            
if             R      IN         less than           R      OUT        ,      xe2x80x83    ⁢            and      ⁢              xe2x80x83            ⁢      K        =                                        M            ·                          R              CLK                                            N            ·                          R              IN                                      ⁢                  xe2x80x83                ⁢        if        ⁢                  xe2x80x83                ⁢                  R          IN                     greater than                         R          OUT                .            
The clock generator is operable to generate a clock signal for controlling the routing circuit and characterized by a non-uniform sequence of pulses having an average period T between successive pulses, given by   T  =            K              R        CLK              .  
In another aspect, the invention features a clocking domain conversion method in accordance with which, N input bits are simultaneously loaded into an input during each load cycle, wherein N has an integer value of at least 1. M output bits are simultaneously outputted from an output during each output cycle at a rate ROUT, wherein M has an integer value of at least 1 and Mxe2x89xa0N. The N input bits are routed from the input to the output at a clocking rate RCLK and with a dividing ratio K of the routing circuit data rate relative to the higher of the input and output data rates, given by       K    =                                        N            ·                          R              CLK                                            M            ·                          R              OUT                                      ⁢                  xe2x80x83                ⁢        if        ⁢                  xe2x80x83                ⁢                  R          IN                     less than               R        OUT              ,
and   K  =                              M          ·                      R            CLK                                    N          ·                      R            IN                              ⁢              xe2x80x83            ⁢      if      ⁢              xe2x80x83            ⁢              R        IN               greater than                   R        OUT            .      
The the routing circuit is controlled with a clock signal characterized by a non-uniform sequence of pulses having an average period T between successive pulses, given by   T  =            K              R        CLK              .  
In another aspect of the invention, a clocking domain conversion system includes an input, an output, a routing circuit, and a clock generator. The input is operable to simultaneously load N input bits during each load cycle, wherein N has an integer value of at least 1. The output is operable to simultaneously output M output bits during each output cycle at a rate ROUT, wherein M has an integer value of at least 1 and Mxe2x89xa0N. The routing circuit is operable to route the N input bits from the input to the output at a clocking rate RCLK. The clock generator is operable to generate an input clock signal for controlling simultaneous loading of the N input bits during each load cycle and characterized by a non-uniform sequence of pulses.
In another aspect of the invention, a clocking domain conversion system includes an input, an output, a routing circuit, and a clock generator. The input is operable to simultaneously load N input bits during each load cycle, wherein N has an integer value of at least 1. The output is operable to simultaneously output M output bits during each output cycle at a rate ROUT, wherein M has an integer value of at least 1 and Mxe2x89xa0N. The routing circuit is operable to route the N input bits from the input to the output at a clocking rate RCLK. The clock generator is operable to generate an output clock signal for controlling simultaneous outputting of the M output bits during each output cycle and characterized by a non-uniform sequence of pulses.